The present disclosure relates generally to the field of semiconductor fabrication. In conventional practice, semiconductor fabrication begins with the provision of a semiconductor wafer, comprising silicon formed in a regular, crystalline structure. A circuit pattern is devised in which regions of the semiconductor wafer are intended to support NMOS and PMOS semiconductor components. These regions are isolated from each other with the formation of electronically inert isolation trenches. Each region is then doped with a type of dopant opposite the electronic nature of the components to be created thereupon. For instance, the dopant may be introduced through ion implantation, in which charged ions of the dopant material are fired at the semiconductor wafer at high speeds, thereby physically injecting them into the substrate. Following doping, electronic components are then formed upon the semiconductor wafer, which typically involves doping (via ion implantation or another suitable method) the electronically active areas of the semiconductor wafer with the desired type of dopant. For instance, NMOS components are formed by placing a p-type dopant in a region of the semiconductor, and then forming the components by placing an n-type dopant in order to create the electronically active regions of the NMOS component. Each dopant is exposed to a thermal anneal, which restores the crystalline lattice structure of the semiconductor wafer (since some physical placement processes, such as ion implantation, can disrupt the crystalline lattice), and also electronically “activates” the dopant ions by positioning them within the same lattice structure. The components may then be connected through a metallization step, in which metal paths are formed to connect the electronically active areas of the components into a fully interconnected circuit.
It will be appreciated that the placement of the dopant is a key step in semiconductor component fabrication. For many semiconductor components, the characteristics of doping, such as the choice of dopant, the placement method, and the resulting concentration and area of the dopant, dopant concentration vertical and lateral gradient, bear critically on the resulting performance and reliability of the components. One scenario that requires precise placement is in the formation of source/drain regions of a MOSFET transistor. A typical transistor comprises two electronically active areas that serve as the source and drain regions of the transistor, which are bridged by a gate. When the gate is powered above a certain threshold voltage, a conductive channel is formed between the source and drain regions to close the circuit; but when the gate is unpowered, the channel resists such electronic flow. In this context, the characteristics of the source/drain region doping relate to the threshold voltage of the gate and the resistance of the channel in powered and unpowered states. If the dopant concentration is too low, or if the source and drain are too distant, the threshold voltage will be undesirably high. If the dopant concentration is too high, or if the source and drain regions are too close, the threshold voltage will be undesirably low, and the resistance in the unpowered state may be insufficient to prevent electron flow.
One challenge that interferes with the precise placement of dopant is the high-temperature thermal anneal. The high temperature is necessary to induce the dopant ions to move into position within the crystalline lattice structure in order to participate in the conductivity of the circuit, which thereby “activates” the dopant. However, the high temperature also promotes diffusion of the dopant material through the solid medium of the semiconductor substrate. Since the dopant is placed at an area of high concentration, diffusion serves to disperse the concentrated dopant ions throughout the undoped adjacent areas of the substrate, thereby creating a broadened, imprecise gradient of doping that compromises the predictability and reliability of the circuit.
The occurrence of thermally induced fusion are well-studied, and are generally presented as a relationship known as Fick's laws of diffusion, shown in FIGS. 1A-1C. FIG. 1A presents Fick's first law of diffusion 10, describing steady-state diffusion, in which J represents diffusion flux, which is equivalent to the rate of net diffusion. This equation 10 demonstrates that diffusion flux is proportional to the constant D, which represents a diffusion coefficient for the substrate. Similarly, FIG. 1B presents Fick's second law of diffusion 12, describing dynamic state diffusion, in which ∂φ/∂t represents the change in concentration over time (which, again, is equivalent to the rate of net diffusion.) This equation 12 also demonstrates that the change in concentration over time is proportional to the constant D. Both equations rely on the calculation of the diffusion coefficient, D, which is performed according to the equation presented in FIG. 1C. In this equation 14, the diffusion coefficient is shown to be proportional to T, which represents the temperature of the substrate. Because the diffusion coefficient of a substrate is proportional to its temperature (according to 14), and because the rate of diffusion is proportional to the diffusion coefficient in both steady-state environments (according to 10) and dynamic-state environments (12), it will be evident that, according to Fick's laws, diffusion of a substance (such as a dopant) in a solid substrate is generally proportional to the temperature of the solid substrate. As a result, higher temperature anneals promote dopant diffusion out of a target area in which the dopant was placed, thereby reducing the performance and reliability of the semiconductor component. This prediction is borne out through common observations and practice in the field of art.
At least two methods are known to reduce diffusion of a dopant placed in a semiconductor substrate. First, the temperature of the semiconductor substrate is often kept low to reduce diffusivity, again in keeping with Fick's laws. For instance, the anneal may be performed at a sufficiently high temperature to activate the dopant, but no greater, in order to limit diffusion that deactivates the dopant. The semiconductor fabrication process may be arranged so that, following the placement of the dopant, the substrate is kept below a certain temperature threshold, which, if exceeded, is believed to cause diffusion to exceed manufacturing tolerances.
A second known technique for reducing diffusion is the placement of carbon (or an agent that contains carbon) in the semiconductor substrate, which is known to suppress diffusion of some dopants during thermal annealing. However, the suppressant aspect of carbon as a co-placement with a dopant is not known to alter the proportionalities of Fick's law, but rather restrains the rates of diffusion otherwise predicted thereby.
A related problem with semiconductor doping that will be addressed herein pertains to a physical characteristic of the semiconductor substrate that causes problems with ion implantation placement. Because the substrate comprises a crystalline lattice with a regular structure, some lattice configurations may include longitudinal channels. If a dopant particle placed via ion implantation is fired at the substrate with an angle and position corresponding to a channel, it may deeply penetrate the substrate before coming to rest in a region of the lattice, resulting in undesirably deep penetration. This characteristic of ion implantation may disrupt the tight control of active area doping, and hence the performance and reliability of semiconductors fabricated in this manner.
In light of the foregoing explanation of source/drain regions and the impact of these designs on transistor performance, it will be appreciated that tight control over the dopant diffusion, placement depth, and channeling through longitudinal channels is advantageous for semiconductor manufacturing. Such control is also desirable due to the trend of increasing miniaturization in electronic components, where the demand for increasingly miniaturized semiconductor components calls for greater precision in fabrication techniques. Therefore, it is always desirable to make improvements in the area of semiconductor fabrication.